Split fin field effect transistor enabling back bias on fin type field effect transistors

ABSTRACT

A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.

BACKGROUND Technical Field

The present disclosure relates to semiconductor devices, such assemiconductor devices including fin structures. The present disclosurefurther relates to processing of fin including structures that includepunch through stop regions.

Description of the Related Art

The dimensions of semiconductor field effect transistors (FETs) havebeen steadily shrinking over the last thirty years or so, as scaling tosmaller dimensions leads to continuing device performance improvements.Planar FET devices typically have a conducting gate electrode positionedabove a semiconducting channel, and electrically isolated from thechannel by a thin layer of gate oxide. Current through the channel iscontrolled by applying voltage to the conducting gate. With conventionalplanar FET scaling reaching fundamental limits, the semiconductorindustry is looking at more unconventional geometries that willfacilitate continued device performance improvements. One such class ofdevice is a fin field effect transistor (FinFET).

SUMMARY

In one aspect, a method of forming a semiconductor device is providedincluding a split portion fin structure and a metal nitride presentcentrally within the split portion of the fin structure to apply a backbias to the semiconductor device. In one embodiment, the method includesforming a trench in a substrate, and forming a metal nitride in thetrench. The method may further include forming a split fin structurefrom the substrate. The metal nitride is positioned in the split portionof the fin structure. The method may continue with removing the metalnitride from a source region and drain region portion of the split finstructure, in which the metal nitride remains in a channel regionportion of the split fin structure. A gate structure may then be formedon a channel region portion of the fin structure.

In another embodiment, the method of forming the semiconductor devicemay include forming a trench in a substrate, and forming a metal nitridein the trench. The method may further include forming a split finstructure from the substrate. The metal nitride is positioned in thesplit portion of the fin structure. The method may continue withremoving the metal nitride from a source region and drain region portionof the split fin structure, in which the metal nitride remains in achannel region portion of the split fin structure. A gate structure maythen be formed on a channel region portion of the fin structure. A backbias is applied to the semiconductor device using the metal nitride inthe split portion of the fin structure as an electrode.

In another aspect of the present disclosure, a semiconductor device isprovided including a metal nitride present centrally within a splitportion of a channel region portion of a fin structure to apply a backbias to the semiconductor device. In one embodiment, the semiconductordevice includes a fin structure comprising a split portion, and a metalnitride positioned in the split portion of a channel region of the finstructure. The semiconductor device may further include a source regionincluding a first end of the split portion of the fin structure thatdoes not include the metal nitride; and a drain region including asecond end of the split portion of the fin structure that does notinclude the metal nitride. The first end and the second end of the splitportion are on opposing sides of the channel region. A gate structure ispresent on the channel region of the fin structure.

BRIEF DESCRIPTION OF DRAWINGS

The following detailed description, given by way of example and notintended to limit the disclosure solely thereto, will best beappreciated in conjunction with the accompanying drawings, wherein likereference numerals denote like elements and parts, in which:

FIG. 1 is a perspective view of one embodiment of a forming a mandrelatop a substrate that is processed to provide fin structures, inaccordance with the present disclosure.

FIG. 2 is a perspective view of forming spacers on the sidewalls of themandrels and etching the substrate using a combination of the spacersand the mandrels as an etch mask, in accordance with one embodiment ofthe present disclosure.

FIG. 3 is a perspective view of depicting forming a high-k dielectriclayer on at least the sidewalls of the trench and forming a dopantregion for back bias contact at the base of the trench, in accordancewith one embodiment of the present disclosure.

FIG. 4 is a perspective view of one embodiment of removing thehorizontal portions of the high-k dielectric layer, forming a metalnitride layer in a lower portion of the trench, and filling the upperportion of the trench with a dielectric cap, in accordance with oneembodiment of the present disclosure.

FIG. 5 is a perspective view depicting removing the mandrels, etchingfin trenches in the semiconductor substrate, forming isolation regionsin the fin trenches, and recessing the isolation regions and thedielectric caps, in accordance with one embodiment of the presentdisclosure.

FIG. 6 is a perspective view depicting forming a sacrificial gatestructure, and removing exposed portions of the dielectric caps, metalnitride layer and high-k dielectric layer, in accordance with oneembodiment of the present disclosure.

FIG. 7 is a perspective view depicting one embodiment of a blanketdeposition of a low-k spacer material on the structure depicted in FIG.6.

FIG. 8 is a perspective view of etching the low-k spacer material toform spacers, in accordance with one embodiment of the presentdisclosure.

FIG. 9 is a perspective view of forming epitaxial semiconductor sourceand drain material, in accordance with one embodiment of the presentdisclosure.

FIG. 10 is a perspective view of forming a dielectric layer over thestructure depicted in FIG. 9 having an upper surface coplanar with theupper surface of the sacrificial gate structure, and removing thesacrificial gate structure, in accordance with one embodiment of thepresent disclosure.

FIG. 11A is a perspective view of forming a high-k metal gate stack inthe gate opening that is produced by removing the sacrificial gatestructure, in accordance with one embodiment of the present disclosure.

FIG. 11B is a perspective view of the cross section of the channelregion of the fin structure depicted in FIG. 11A.

FIG. 12A is a perspective view of forming a gate material fill thatfills the gate opening that is depicted in FIG. 11A, in accordance withone embodiment of the present disclosure.

FIG. 12B is a perspective view of the cross section of the channelregion of the fin structure depicted in FIG. 12A.

FIG. 13 is a top down view depicting of one embodiment of asemiconductor device formed in accordance with the method described withreference to FIGS. 1-12B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Detailed embodiments of the claimed structures and methods are disclosedherein; however, it is to be understood that the disclosed embodimentsare merely illustrative of the claimed structures and methods that maybe embodied in various forms. In addition, each of the examples given inconnection with the various embodiments is intended to be illustrative,and not restrictive. Further, the figures are not necessarily to scale,some features may be exaggerated to show details of particularcomponents. Therefore, specific structural and functional detailsdisclosed herein are not to be interpreted as limiting, but merely as arepresentative basis for teaching one skilled in the art to variouslyemploy the methods and structures of the present disclosure. Forpurposes of the description hereinafter, the terms “upper”, “lower”,“right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the embodiments of the disclosure,as it is oriented in the drawing figures. The terms “positioned on”means that a first element, such as a first structure, is present on asecond element, such as a second structure, wherein interveningelements, such as an interface structure, e.g. interface layer, may bepresent between the first element and the second element. The term“direct contact” means that a first element, such as a first structure,and a second element, such as a second structure, are connected withoutany intermediary conducting, insulating or semiconductor layers at theinterface of the two elements.

In some embodiments, the methods and structures disclosed herein form aFinFET semiconductor device including a punch through stop region. Afield effect transistor (FET) is a semiconductor device in which outputcurrent, i.e., source-drain current, is controlled by the voltageapplied to a gate structure to the semiconductor device. A field effecttransistor has three terminals, i.e., gate structure, source region anddrain region. As used herein, a “fin structure” refers to asemiconductor material, which is employed as the body of a semiconductordevice, in which the gate structure is positioned around the finstructure such that charge flows down the channel on the two sidewallsof the fin structure and optionally along the top surface of the finstructure. A FinFET is a semiconductor device that positions the channelregion of the semiconductor device in a fin structure. The source anddrain regions of the fin structure are the portions of the fin structurethat are on opposing sides of the channel region of the fin structure.

It has been determined that back bias can be useful in deviceperformance, such as high performance FinFET device performance.Traditionally, planar semiconductor devices have been able to takeadvantage of back biasing the device in conjunction with being formed onsemiconductor on insulator (SOI) substrates. However, it has beendifficult to apply back bias to Fin type Field Effect Transistors(FinFETs). It has been determined that with typical FinFETs that backbiasing a fin structure at the base of the fin that contacts thesupporting substrate does not effectively bias the entire channelportion of the fin, i.e., the fin has a height that is too great to beeffectively biased using back bias applied from an underlying substrate.Typically, the top to middle portions of the fin are inadequately backbiased using conventional methods. As will be further described below,the methods and structures disclosed herein enables effective back biasin fin structures through the entire channel, i.e., effective back biasof an entire height of the channel region in the fin structures, whichis suitable for use with fin structures on bulk semiconductor substrateand semiconductor on insulator (SOI) substrates. The methods andstructures of the present disclosure are now described with greaterdetail referring to FIGS. 1-13.

FIG. 1 illustrates one embodiment of a forming a mandrel 5 atop asubstrate 1 that is processed to provide fin structures. In theembodiment, the semiconductor substrate 1 is composed of intrinsicsemiconductor material, i.e., not an n-type or p-type doped material. Insome embodiments, the semiconductor substrate 1 may be composed of atype IV or type III-V semiconductor material. By “type IV semiconductor”it is meant that the semiconductor material includes at least oneelement from Group IVA (i.e., Group 14) of the Periodic Table ofElements. Examples of type IV semiconductor materials that are suitablefor the fin structure include silicon (Si), germanium (Ge), silicongermanium (SiGe), silicon doped with carbon (Si:C), silicon germaniumdoped with carbon (SiGe:C) and a combination thereof. A compoundsemiconductor may be a III-V semiconductor material or a type II/VIsemiconductor material. By “III-V semiconductor material” it is meantthat the semiconductor material includes at least one element from GroupIIIA (i.e., Group 13) of the Periodic Table of Elements and at least oneelement from Group VA (i.e., Group 15) of the Periodic Table ofElements. Examples of compound semiconductor materials that are suitablefor the fin structures 10 include at least one of aluminum antimonide(AlSb), aluminum arsenide (AlAs), aluminum nitride (AlN), aluminumphosphide (AlP), gallium arsenide (GaAs), gallium phosphide (GaP),indium antimonide (InSb), indium arsenic (InAs), indium nitride (InN),indium phosphide (InP), aluminum gallium arsenide (AlGaAs), indiumgallium phosphide (InGaP), aluminum indium arsenic (AnnAs), aluminumindium antimonide (AlInSb), gallium arsenide nitride (GaAsN), galliumarsenide antimonide (GaAsSb), aluminum gallium nitride (AlGaN), aluminumgallium phosphide (AlGaP), indium gallium nitride (InGaN), indiumarsenide antimonide (InAsSb), indium gallium antimonide (InGaSb),aluminum gallium indium phosphide (AlGaInP), aluminum gallium arsenidephosphide (AlGaAsP), indium gallium arsenide phosphide (InGaAsP), indiumarsenide antimonide phosphide (InArSbP), aluminum indium arsenidephosphide (AlInAsP), aluminum gallium arsenide nitride (AlGaAsN), indiumgallium arsenide nitride (InGaAsN), indium aluminum arsenide nitride(InAlAsN), gallium arsenide antimonide nitride (GaAsSbN), gallium indiumnitride arsenide aluminum antimonide (GaInNAsSb), gallium indiumarsenide antimonide phosphide (GaInAsSbP), and combinations thereof.

The semiconductor substrate 1 may be a bulk substrate, as depicted inFIG. 1, or the semiconductor substrate may be a semiconductor oninsulator (SOI) substrate. The substrate 1 may have a dopant region 2(e.g. punch through stopper). The punch through stopper has n-typedopant for PFET, or has p-type dopant for NFET. The dopant region 2 canbe for the back bias contact, which is composed of an n-type or p-typedopant that may be implanted into the substrate 1. The term“conductivity type” denotes whether are region of the device is doped toan n-type or p-type conductivity. As used herein, “p-type” refers to theaddition of impurities to an intrinsic semiconductor that createsdeficiencies of valence electrons. In a type IV semiconductor, such as asilicon-containing semiconductor material, examples of n-type dopants,i.e., impurities, include but are not limited to: boron, aluminum,gallium and indium. As used herein, “n-type” refers to the addition ofimpurities that contributes free electrons to an intrinsicsemiconductor. In a type IV semiconductor, such as a silicon containingsemiconductor material, examples of n-type dopants, i.e., impurities,include but are not limited to antimony, arsenic and phosphorous. Thedopant region 2 may be formed using ion implantation. The substrate 1could also have a well region 3 that has the same type of dopant withthe dopant region 2 but less dopant concentration than that of thedopant region 2. In one example, the dopant region 2 could have dopantconcentration 2×10¹⁸ cm⁻³ to 1×10¹⁹ cm⁻³, while the well region 3 couldhave be un-doped to dopant concentration 1×10¹⁸ cm⁻³. An SOI substratetypically includes an upper semiconductor layer, which may be referredto as an SOI layer; a dielectric layer underlying the uppersemiconductor layer, which may be referred to as a buried oxide layer(BOX); and a base substrate (also referred to as supporting substrate)of a semiconductor material underlying the dielectric layer.

Forming the mandrels 5 atop the semiconductor substrate can includeforming a mandrel material layer on the material layer of thesemiconductor substrate 1 that provides the fin structures. The mandrelmaterial layer can include any material (semiconductor, dielectric orconductive) that can be selectively removed from the structure during asubsequently performed etching process. In one embodiment, the mandrelmaterial layer 5 may be composed of amorphous silicon or polysilicon. Inanother embodiment, the mandrel material layer 5 may be composed of ametal, such as, e.g., aluminum (Al), tungsten (W), or copper (Cu). Themandrel material layer can be formed by a deposition method, such aschemical vapor deposition or plasma enhanced chemical vapor deposition.In one embodiment, the thickness of the mandrel material layer can befrom 50 nm to 300 nm. Following deposition of the mandrel materiallayer, the mandrel material layer can be patterned by lithography andetching to form a plurality of mandrel structures 5 on the topmostsurface of the semiconductor substrate 1.

The mandrels 5 may have a width W1 ranging from 10 nm to 60 nm. In someembodiments, the mandrels 5 may have a width W2 ranging from 15 nm to 50nm. The term “pitch” denotes the center to center distance separatingadjacent structures, e.g., repeating adjacent structures. In theembodiment that is depicted in FIG. 1, the mandrels may be separated bya pitch P1 ranging from 30 nm to 80 nm. In another embodiment, themandrels may be separated by a pitch P1 ranging from 35 nm to 70 nm.

FIG. 2 depicts one embodiment of forming spacers 10 on the sidewalls ofthe mandrels 5 and etching the substrate 5 using a combination of thespacers 10 and the mandrels as an etch mask. The spacers 10 may beformed by deposition of a dielectric spacer material, and then etchingthe deposited dielectric spacer material. The dielectric spacer materialmay comprise any dielectric spacer material such as, for example,silicon dioxide, silicon nitride or a dielectric metal oxide. In oneexample, the dielectric spacer material is silicon nitride. Examples ofdeposition processes that can be used in providing the dielectric spacermaterial include, but are not limited to, chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), or atomiclayer deposition (ALD). Examples of etching that be used in providingthe dielectric spacers 10 include any etching process, such as, e.g.,reactive ion etching (RIE). The spacers 10 may have a width W2 rangingfrom 1 nm to 10 nm. For example, the spacers 10 may have a width W2 onthe order of 5 nm.

Still referring to FIG. 2, following formation of the spacers 10, atrench 15 may be formed in the semiconductor substrate 1 with an etchprocess that employs the spacers 10 and the mandrels 5 as an etch mask.In some embodiments, the bottom of the trench 15 reaches or is insidethe dopant region 2 (e.g. punch through stopper region). The etchprocess for forming the trench 15 may be an anisotropic etch, such asreactive ion etch (RIE). Other etch processes that are suitable for thisstage of the present disclosure may include gas plasma etching and laseretching. In some embodiments, the etch process for etching the trench 10is selective to the mandrels 5 and the spacers 10. The term “selective”as used to describe a material removal process denotes that the rate ofmaterial removal for a first material is greater than the rate ofremoval for at least another material of the structure to which thematerial removal process is being applied. For example, in oneembodiment, a selective etch may include an etch chemistry that removesa material of the semiconductor substrate 1 selectively to the mandrels5 and spacers 10 by a ratio of 10:1 or greater, e.g., 100:1 or greater.

The trench 10 may have a width W3 ranging from 5 nm to 20 nm, and adepth D1 ranging from 30 nm to 100 nm. In one example, the trench 10 hasa width of approximately 10 nm and a depth D1 of approximately 50 nm.

FIG. 3 depicts one embodiment of forming a high-k dielectric layer 20 onthe sidewalls of the trench 15 and using the dopant region 2 for backbias contact at the base of the trench 15. The term “high-k” denotes adielectric material having a dielectric constant greater than siliconoxide (SiO₂) at room temperature (20° C. to 25° C.) and atmosphericpressure (1 atm). For example, a high-k dielectric layer 20 may have adielectric constant greater than 4.0. In another example, the high-kgate dielectric layer 20 has a dielectric constant greater than 7.0. Inone embodiment, the high-k gate dielectric layer 20 may be composed of ahigh-k oxide, such as, for example, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃,SrTiO₃, LaAlO₃, Y₂O₃ and mixtures thereof. Other examples of high-kdielectric materials for the high-k gate dielectric layer 20 includehafnium silicate, hafnium silicon oxynitride or combinations thereof.

The high-k dielectric layer 20 is typically a conformally formed layerthat is formed on the sidewalls of the trench 15 provided by the etchedportion of the substrate 1 and the sidewalls of the spacers 10. Theseportions of the conformally formed high-k dielectric layer 20 may bereferred to as vertically orientated portions. The high-k dielectriclayer 20 is also formed on the base of the trench 15, as well as theupper surfaces of the spacers 20 and the mandrels 5. These portions ofthe conformally formed high-k dielectric layer 20 may be referred to aslaterally orientated portions. The vertically orientated portions andlaterally orientated portions of the high-k dielectric layer 20 may beprovided by a continuous layer. The term “conformal” denotes a layerhaving a thickness that does not deviate from greater than or less than30% of an average value for the thickness of the layer. In oneembodiment, the high-k gate dielectric layer 20 may be deposited bychemical vapor deposition (CVD). Variations of CVD processes suitablefor depositing the high-k dielectric layer 20 include, but are notlimited to, atomic pressure chemical vapor deposition (APCVD), lowpressure chemical vapor deposition (LPCVD), plasma enhanced chemicalvapor deposition (PECVD), metal organic chemical vapor deposition(MOCVD), atomic layer deposition (ALD), and combinations thereof. In oneembodiment, the thickness of the high-k dielectric layer 20 is greaterthan 0.8 nm. More typically, the high-k dielectric layer 20 has athickness ranging from about 1.0 nm to about 6.0 nm.

FIG. 4 depicts one embodiment of removing the horizontal portions of thehigh-k dielectric layer 20, forming a metal nitride layer 30 in a lowerportion of the trench 15, and filling the upper portion of the trenchwith a dielectric cap 35. Removing the horizontal portions of the high-kdielectric layer 20 may include an etch process, such as gas cluster ionbeam (GCIB) etching. It is noted that this is only one example of anetch process that can be used at this step of the process flow. The etchprocess for removing the horizontal portions of the high-k dielectriclayer 20 may include any wet or dry etch. In some embodiments, the etchprocess may be selective to the mandrel 5 and the semiconductorsubstrate 1. In some examples, the etch process may be an anisotropicetch. For example, alternative etch processes that can be used at thisstage of the process flow can include reactive ion etch, plasma etch,laser etching, laser ablation, and combinations thereof.

In a following process step, the metal nitride 30 may be deposited atleast filling a portion of the trench 15. For example, the metal nitride30 may be provided by titanium nitride (TiN). Other examples of metalnitrides 30 that can be used at this stage of the present disclosure mayinclude tantalum nitride (TaN), tungsten nitride (WN), tantalum siliconnitride (TaSiN) and combinations thereof. In other embodiment, the metalnitride 30 may be substituted with an elemental metal layer, such as Al,Mo, W, Ta, Ti, Cu, Pt and combinations thereof. The metal nitride 30 maybe blanket deposited and may completely fill the trenches 15 with aportion of the metal nitride 30 extending onto the upper surfaces of themandrel 5 and the spacers 10. The metal nitride layer 30 may bedeposited using chemical vapor deposition (CVD) or physical vapordeposition (PVD). Examples of PVD that are suitable for forming themetal nitride layer 30 include plating, electroplating, electrolessplating, sputtering and combinations thereof. Examples of chemical vapordeposition (CVD) suitable for forming the metal nitride layer 30 mayinclude metal organic chemical vapor deposition (MOCVD) or plasmaenhanced chemical vapor deposition (PECVD).

In some embodiments, the metal nitride 30 may be recessed within thetrench using an etch process so that the upper surface of the recessedmetal nitride 30 is below an upper surface of the semiconductorsubstrate 1. For example, the metal nitride 30 may be recessed until theupper surface of the metal nitride 30 is below and vertically offsetfrom the upper surface of the semiconductor substrate 1 by a dimensionranging from 1 nm to 20 nm. In another example, the metal nitride 30 maybe recessed until the upper surface of the metal nitride 30 is below andvertically offset from the upper surface of the semiconductor substrate1 by a dimension ranging from 5 nm to 10 nm. The etch process forrecessing the metal nitride 30 can be selective to the mandrels 5, aswell as the spacers 10. The etch process for recessing the metal nitride30 may be a dry process or a wet process. For example, the etch processmay include wet chemical etching, reactive ion etching, gas cluster ionbeam (GCIB) etching or a combination thereof.

Still referring to FIG. 4, a dielectric cap 35 is formed atop therecessed metal nitride 30 filling the trench 15. The dielectric cap 35may be composed of any dielectric material, such as an oxide, nitride oroxynitride material. In some embodiments, when the dielectric cap 35 iscomposed of a nitride, the nitride may be silicon nitride. Thedielectric cap 35 may be deposited using a chemical vapor deposition(CVD) process. For example, the CVD process for forming the dielectriccap 35 may include atomic pressure chemical vapor deposition (APCVD),low pressure chemical vapor deposition (LPCVD), plasma enhanced chemicalvapor deposition (PECVD), metal organic chemical vapor deposition(MOCVD), atomic layer deposition (ALD) or a combination thereof. In someembodiments, to provide that the upper surface of the dielectric cap 35is coplanar with the upper surface of the mandrel 5, the dielectric cap35 may be planarized using a planarization process, such as grinding orchemical mechanical planarization.

FIG. 5 depicts one embodiment of a structure that is produced by aprocess flow that includes removing the mandrels 5; etching fin trenches45 in the semiconductor substrate 1; forming isolation regions 50 in thefin trenches; and recessing the isolation regions 50 and the dielectriccaps 35. The mandrels 5 may be removed using a selective etch process.For example, the mandrels 5 may be removed by an etch process thatremoves the mandrels selectively to the spacers 10, the high-kdielectric 20, and the dielectric cap 35. The etch process for removingthe mandrels 5 may also be selective to the semiconductor substrate 1.The etch process for removing the mandrels 5 may be a wet etch or a dryetch. One example of a wet etch for removing the mandrels is a wetchemical etch. Dry etch process for removing the mandrels 5 may includereactive ion etch (RIE) and plasma etching.

Following removing the mandrels 5, the fin structures 45 may bepatterned by etching the semiconductor substrate 1 using the spacers 10and the dielectric cap 35 as an etch mask. The etch process for formingthe fin structures 45 may be an anisotropic etch process. For example,the anisotropic etch process for forming the fin structures 45 mayinclude reactive ion etch (RIE), plasma etching, ion beam etching orlaser ablation. The etch process is continued until the semiconductorsubstrate 1 is etched to a depth suitable for providing the selectedheight of the fin structures 45. In some embodiments, the fin structures45 may have a height ranging from 5 nm to 200 nm. In another embodiment,the fin structures 45 may have a height ranging from 10 nm to 100 nm. Inone example, the fin structures 45 may have a height ranging from 20 nmto 50 nm. The fin structures 45 may have a width of less than 20 nm. Inanother embodiment, the fin structures 45 may have a width ranging from3 nm to 8 nm.

As depicted in FIG. 5, each of the fin structures 45 includes an upperportion having a centrally positioned metal nitride 30. The positioningof the centrally positioned metal nitride 30 that is flanked by splitupper portions of the fin structure 45 illustrate a “split” finstructure. As depicted in FIG. 5, the centrally positioned metal nitride30 can be separated from the split portion of the fin structure 45 byportions of the high-k dielectric layer 20.

Following patterning of the semiconductor substrate 1 to provide the finstructures 45, the fin structure trenches 45 may be filled with adielectric material for forming isolation regions 50 between adjacentfin structures 45. The dielectric material may be deposited in the finstructure trenches using deposition processes, such as chemical vapordeposition (CVD). The dielectric material may be an oxide, nitride oroxynitride material. For example, the dielectric material that isdeposited in the trenches between adjacent fin structures may becomposed of silicon oxide. In some embodiments, the dielectric materialthat is deposited for the isolation regions 50 may be deposited to adepth that entirely fills the trenches separating adjacent finstructures.

In some embodiments, the method may continue with planarizing thestructure stopping on the upper surface of the fin structures 45, asdepicted in FIG. 5. The planarization process may be provided bygrinding or chemical mechanical planarization (CMP). The planarizationstep may remove the entirety of the spacers 10. A portion of thedielectric cap 35 may remain atop the metal nitride material 30. In someembodiments, at this stage of the process flow the upper surface of thedielectric material in the isolation region 50 may be coplanar with theupper surface of the fin structures 45 and the upper surface of theremaining portion of the dielectric cap 35.

In a following process step, a fin reveal etch may be conducted thatrecesses the dielectric material that provides the isolation regions 50.The dielectric material for the isolation regions 50 may be recessedusing an etch process that removes the dielectric material for theisolation regions 50 selectively to the fin structure 45, the high-kdielectric layer 20 and the dielectric cap 35. The etch process forrevealing the fin structures may be a dry process or a wet process. Forexample, the etch process may be anisotropic, and selected from reactiveion etch (RIE), plasma etching, laser ablation and combinations thereof.In some embodiment, the length L1 of the sidewall of the fin structures45 revealed by this etch process may range from 15 nm to 40 nm.

FIG. 6 depicts forming a sacrificial gate structure 55, and removingexposed portions of the dielectric caps 35, metal nitride layer 30 andhigh-k dielectric layer 20. The term “sacrificial” as used to describethe sacrificial gate structure 55 depicted in FIG. 6 denotes that thestructure is present during the process sequence, but is not present inthe final device structure, in which the sacrificial gate structure 55provides an opening that dictates the size and geometry of a laterformed functional gate conductor. The sacrificial material that providesthe sacrificial gate structure 55 may be composed of any material thatcan be etched selectively to the underlying fin structure 45 and metalnitride layer 35. In one embodiment, the sacrificial material thatprovides the sacrificial gate structure 55 may be composed of asilicon-containing material, such as polysilicon. Although, thesacrificial gate structure 55 is typically composed of a semiconductormaterial, the sacrificial gate structure 55 may also be composed of adielectric material, such as an oxide, nitride or oxynitride material,or amorphous carbon.

The sacrificial material may be patterned and etched to provide thesacrificial gate structure 55. Specifically, and in one example, apattern is produced by applying a photoresist to the surface to beetched, exposing the photoresist to a pattern of radiation, and thendeveloping the pattern into the photoresist utilizing a resistdeveloper. Once the patterning of the photoresist is completed, thesections if the sacrificial material covered by the photoresist areprotected to provide the sacrificial gate structure 55, while theexposed regions are removed using a selective etching process thatremoves the unprotected regions. Following formation of sacrificial gatestructure 55, the photoresist may be removed.

FIG. 6 also depicts one embodiment of removing the portions of thedielectric caps 35, the metal nitride layer 30 and the high-k dielectriclayer 20 that correspond to the source and drain region portions of thefin structure 45. The portion of the dielectric caps 35, the metalnitride layer 30 and the high-k dielectric layer 20 that are present inthe channel portion of the fin structure 45 remain and are protected bythe sacrificial gate structure 55, which functions as an etch mask.

The dielectric caps 35, the metal nitride layer 30 and the high-kdielectric layer 20 that are present in the source and drain regionportions of the fin structures 45 may be removed with an etch processthat is selective to the fin structures 45 and the sacrificial gatestructure 55. The etch process may include reactive-ion etching (RIE).Reactive Ion Etching (RIE) is a form of plasma etching in which duringetching the surface to be etched is placed on the RF powered electrode.Moreover, during RIE the surface to be etched takes on a potential thataccelerates the etching species extracted from plasma toward thesurface, in which the chemical etching reaction is taking place in thedirection normal to the surface. Other examples of etch processes thatcan be used at this point of the present disclosure include ion beametching, plasma etching or laser ablation.

FIG. 7 depicts one embodiment of a blanket deposition of a low-k spacermaterial 60 on the structure depicted in FIG. 6. The low-k spacermaterial 60 can typically have a dielectric constant that is less than4.0, e.g., 3.9. In one embodiment, the low-k spacer material 60 can havea dielectric constant ranging from 1.75 to 3.5. In another embodiment,the low-k spacer material 60 has a dielectric constant ranging from 2.0to 3.2. In yet an even further embodiment, the low-k spacer material 60has a dielectric constant ranging from 2.25 to 3.0. Examples ofmaterials suitable for the low-k spacer material 60 includeorganosilicate glass (OSG), fluorine doped silicon dioxide, carbon dopedsilicon dioxide, boron doped silicon carbon nitride (SiBCN), carbondoped silicon oxynitride (SiOCN), porous silicon dioxide, porous carbondoped silicon dioxide, spin-on organic polymeric dielectrics (e.g.,SILK™.), spin-on silicone based polymeric dielectric (e.g., hydrogensilsesquioxane (HSQ) and methylsilsesquioxane (MSQ), and combinationsthereof.

The low-k spacer material 60 may be deposited using chemical vapordeposition methods, such as atomic pressure chemical vapor deposition(APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhancedchemical vapor deposition (PECVD), metal organic chemical vapordeposition (MOCVD), atomic layer deposition (ALD), and combinationsthereof. In other embodiments, the low-k spacer material 60 may bedeposited using spin on deposition.

FIG. 8 depicts one embodiment of etching the low-k spacer material 60 toform spacers 65 that are present on sidewalls of the sacrificial gatestructure 55. In some embodiments, a portion of the low-k spacermaterial 65 remains in the space between the split portion of the finstructures 45 having an upper surface substantially coplanar with anupper surface of the isolation regions. Recessing this portions of thefins provides a fin reveal for the epitaxial growth surfaces for formingthe source and drain regions. The spacers 65 may be patterned from thelow-k spacer material 60 using an anisotropic etch process, such asreactive ion etch.

FIG. 9 depicts one embodiment of forming epitaxial semiconductor sourceand drain material 70 on the exposed portions of the fin structures 45.The epitaxial semiconductor source and drain material 70 may be acomponent of the source and drain regions of the device. Source anddrain regions may be present on opposing sides of the channel portion ofthe fin structure 10. As used herein, the term “source” is a dopedregion in the semiconductor device, in which majority carriers areflowing into the channel. As used herein, the term “channel” is theregion underlying the gate structure, e.g., channel portion of the finstructure 10, and between the source and drain of a semiconductor devicethat becomes conductive when the semiconductor device is turned on. Asused herein, the term “drain” means a doped region in semiconductordevice located at the end of the channel, in which carriers are flowingout of the transistor through the drain.

The source and drain regions are typically doped with a conductivitytype dopant that dictates the conductivity type of the device. Forexample, when the source and drain regions are doped to an n-typeconductivity, the semiconductor device is an n-type device, such as ann-type field effect transistor (nFET), e.g., n-type FinFET. In anotherexample, when the source and drain regions are doped to a p-typeconductivity, the semiconductor device is a p-type device, such as ap-type field effect transistor (pFET), e.g., p-type FinFET.

As depicted in FIG. 9, the epitaxial source and drain material 70 isalso formed atop the remaining portion of the low-k spacer material 65that is present in the space between the split portions of the finstructures 45. The term “epitaxial” when referring the source and drainregions denotes that the semiconductor material is formed using anepitaxial deposition process. “Epitaxial growth and/or deposition” meansthe growth of a semiconductor material on a deposition surface of asemiconductor material, in which the semiconductor material being grownhas substantially the same crystalline characteristics as thesemiconductor material of the deposition surface. In some embodiments,when the chemical reactants are controlled and the system parameters setcorrectly, the depositing atoms arrive at the deposition surface withsufficient energy to move around on the surface and orient themselves tothe crystal arrangement of the atoms of the deposition surface. Thus, anepitaxial film deposited on a {100} crystal surface will take on a {100}orientation.

In some embodiments, the epitaxial source and drain material 70 may becomposed of a silicon containing material. For example, the epitaxialsource and drain material 70 may be composed of silicon (Si). In otherembodiments, the epitaxial source and drain material 70 are composed ofa silicon carbon alloy (e.g., silicon doped with carbon (Si:C), silicongermanium, a silicon germanium and carbon alloy (e.g., silicon germaniumdoped with carbon (SiGe:C), silicon alloys, germanium, germanium alloys,gallium arsenic, indium arsenic, indium phosphide, as well as III/V andII/VI compound semiconductors. In another embodiment, the epitaxialsource and drain material 70 are composed of silicon doped withphosphorus (Si:P), or silicon doped with carbon and phosphorus (SiC:P).

A number of different sources may be used for the epitaxial depositionof the epitaxial source and drain material 70. For example, a siliconincluding semiconductor material may be deposited from a siliconincluding source gas that is selected from the group consisting ofsilane, disilane, trisilane, tetrasilane, hexachlorodisilane,tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane,dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane,hexamethyldisilane and combinations thereof. Examples of germaniumincluding source gasses for germanium including semiconductor materialsinclude germane, digermane, halogermane, dichlorogermane,trichlorogermane, tetrachlorogermane and combinations thereof. Thetemperature for epitaxial deposition typically ranges from 450° C. to900° C. Although higher temperature typically results in fasterdeposition, the faster deposition may result in crystal defects and filmcracking.

The dopant that dictates the conductivity type of the epitaxial sourceand drain material 70, which provides the source and drain regions ofthe device, may be implanted into the epitaxial semiconductor materialthat provides the epitaxial source and drain material 70 in situ. Theterm “in situ” denotes that the dopant, e.g., n-type or p-type dopant,is introduced to the base semiconductor material, e.g., silicon orsilicon germanium, during the formation of the base material. Forexample, an in situ doped epitaxial semiconductor material may introducen-type or p-type dopants to the material being formed during theepitaxial deposition process that includes n-type or p-type sourcegasses. In one embodiment, the n-type gas dopant source may includearsine (AsH₃), phosphine (PH₃) and alkylphosphines, such as with theempirical formula R_(x)PH_((3-x)), where R=methyl, ethyl, propyl orbutyl and x=1, 2 or 3. Alkylphosphines include trimethylphosphine((CH₃)₃P), dimethylphosphine ((CH₃)₂PH), triethylphosphine ((CH₃CH₂)₃P)and diethylphosphine ((CH₃CH₂)₂PH). The p-type gas dopant source mayinclude diborane (B₂H₆).

FIG. 10 is a perspective view of forming an interlevel dielectric layer75 over the structure depicted in FIG. 9 having an upper surfacecoplanar with the upper surface of the sacrificial gate structure 55,and removing the sacrificial gate structure 55. Removing the sacrificialgate structure 55 may begin with forming an interlevel dielectric layer75 overlying the structure, and planarizing the interlevel dielectriclayer 75 to be coplanar with an upper surface of the sacrificial gatestructure 55. The sacrificial gate structure 55 may then be removed byan etch that is selective to the fin structures 45 (including theremaining portion of the metal nitride), the high-k dielectric layer 20,and the interlevel dielectric layer. Removing the sacrificial gatestructure 55 provides a gate structure opening to the channel regionportion of the fin structures 45. The method may continue with forming afunctional gate structure 30 in the gate structure opening. The“functional gate structure” operates to switch the semiconductor devicefrom an “on” to “off” state, and vice versa. The functional gatestructure typically includes a high-k metal gate stack 80 and at leastone gate conductor fill 85, as depicted in FIGS. 11A-12B.

FIGS. 11A and 11B depict forming a high-k metal gate stack 80 in thegate opening that is produced by removing the sacrificial gate structure55. The high-k metal gate stack 80 may include a high-k gate dielectricthat is formed directly on the channel region portion of the finstructures 45, and a work function adjusting metal layer, i.e., p-typework function metal layer or n-type work function metal layer.

The term “high-k” as used to describe the material of the high-k gatedielectric of the high-k metal gate stack 80 denotes a dielectricmaterial having a dielectric constant greater than silicon oxide (SiO2)at room temperature (20° C. to 25° C.) and atmospheric pressure (1 atm).For example, a high-k dielectric material may have a dielectric constantgreater than 4.0. In another example, the high-k gate dielectric has adielectric constant greater than 7.0. In one embodiment, the high-k gatedielectric is composed of a high-k oxide, such as, for example, HfO₂,ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ and mixtures thereof.Other examples of high-k dielectric materials for the high-k gatedielectric include hafnium silicate, hafnium silicon oxynitride orcombinations thereof. In one embodiment, the high-k gate dielectric maybe deposited by chemical vapor deposition (CVD). Variations of CVDprocesses suitable for depositing the high-k gate dielectric include,but are not limited to, APCVD, LPCVD, PECVD, MOCVD, ALD, andcombinations thereof. In one embodiment, the thickness of the high-kgate dielectric is greater than 0.8 nm. More typically, the high-k gatedielectric has a thickness ranging from about 1.0 nm to about 6.0 nm.

The work function adjusting metal layer is deposited on the high-k gatedielectric and may be a p-type work function metal layer or an n-typework function metal layer. As used herein, a “p-type work function metallayer” is a metal layer that effectuates a p-type threshold voltageshift. In one embodiment, the work function of the p-type work functionmetal layer ranges from 4.9 eV to 5.2 eV. As used herein, “thresholdvoltage” is the lowest attainable gate voltage that will turn on asemiconductor device, e.g., transistor, by making the channel of thedevice conductive. The term “p-type threshold voltage shift” as usedherein means a shift in the Fermi energy of a p-type semiconductordevice towards a valence band of silicon in the silicon containingsubstrate of the p-type semiconductor device. A “valence band” is thehighest range of electron energies where electrons are normally presentat absolute zero. As used herein, an “n-type work function metal layer”is a metal layer that effectuates an n-type threshold voltage shift.“N-type threshold voltage shift” as used herein means a shift in theFermi energy of an n-type semiconductor device towards a conduction bandof silicon in a silicon-containing substrate of the n-type semiconductordevice. The “conduction band” is the lowest lying electron energy bandof the doped material that is not completely filled with electrons. Inone embodiment, the work function of the n-type work function metallayer ranges from 4.1 eV to 4.3 eV.

In one embodiment, the p-type work function metal layer may be composedof titanium and their nitrided/carbide. In one embodiment, the p-typework function metal layer is composed of titanium nitride (TiN). Thep-type work function metal layer may also be composed of TiAlN, Ru, Pt,Mo, Co and alloys and combinations thereof. In one embodiment, thep-type work function metal layer comprising titanium nitride (TiN) maybe deposited by a physical vapor deposition (PVD) method, such assputtering. Examples of sputtering apparatus that may be suitable fordepositing the p-type work function metal layer include DC diode typesystems, radio frequency (RF) sputtering, magnetron sputtering, andionized metal plasma (IMP) sputtering. In addition to physical vapordeposition (PVD) techniques, the p-type work function metal layer mayalso be formed using chemical vapor deposition (CVD) and atomic layerdeposition (ALD).

In one embodiment, the n-type work function metal layer is composed ofat least one of TiAl, TanN, TiN, HfN, HfSi, or combinations thereof. Then-type work function metal layer can be deposited using chemical vapordeposition (CVD), atomic layer deposition (ALD), sputtering or plating.In one embodiment, the n-type work function metal layer is composed oftitanium aluminum (TiAl) and is deposited using sputtering. Examples ofsputtering apparatus that may be suitable for depositing the n-type workfunction metal layer include DC diode type systems, radio frequency (RF)sputtering, magnetron sputtering, and ionized metal plasma (IMP)sputtering. In one example, an n-type work function metal layer composedof TiN is sputtered from a solid titanium target, in which the nitrogencontent of the metal nitride layer is introduced by a nitrogen gas. Inanother example, an n-type work function metal layer composed of TiN issputtered from a solid target comprised of titanium and nitrogen. Inaddition to physical vapor deposition (PVD) techniques, the n-type workfunction metal layer may also be formed using chemical vapor deposition(CVD) and atomic layer deposition (ALD).

FIG. 11B is a perspective view of the cross section of the channelregion of the fin structure depicted in FIG. 11A. As clearly depicted inFIG. 11B, the high-k metal gate stack 80 is present directly on a splitportion of the fin structures, in which a remaining portion of the metalnitride 30 is centrally positioned in the channel region. The metalnitride 30 positioned in the channel portion of the fin structures 45provides an electrode for enabling back bias of the FinFET. The metalnitride 30 is in contact at the bottom with dopant region 2. Dopantregion 2 can be biased using the back bias contact 90 which is shown onFIG. 13. Since the dopant region 2 has a dopant concentration 2×10¹⁸cm⁻³ to 1×10¹⁹ cm⁻³ which is sufficiently high for the voltage acrossthe dopant region 2 equal to the back bias applied on the back biascontact 90. As the metal nitride 30 is in contact at the bottom withdopant region 2, the metal nitride 30 should have the same voltage tothe dopant region 2 which voltage is equal to the back bias contact 90.The voltage on the metal nitride 30 is the back bias voltage for thechannel fin portion 45, and the voltage is uniform across the metalnitride 45 in the Y-axis thus the back bias voltage across the channelfin portion 45 is uniform. Still referring to FIG. 11B, the electrodeprovided by the metal nitride 30 is separated from the split finportions 45 of the fin structures 45 by the high-k dielectric layer 20.

FIGS. 12A and 12B depict one embodiment of forming a gate material fill85 that fills the gate opening that is depicted in FIGS. 11A and 11B.The gate material fill 85 may be composed of a metal or a dopedsemiconductor. The gate material fill 85 may be formed using adeposition process. In one embodiment, when the gate material fill 85 iscomposed of a metal, the gate material fill 85 is formed using aphysical vapor deposition (PVD) process, such as sputtering. Examples ofsputtering apparatus that may be suitable for depositing the gatematerial fill 85 include DC diode type systems, radio frequency (RF)sputtering, magnetron sputtering, and ionized metal plasma (IMP)sputtering. Metals suitable for the gate material fill 85 includetungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al)and alloys thereof.

FIG. 13 is a top down view depicting of one embodiment of asemiconductor device formed in accordance with the method described withreference to FIGS. 1-12B. FIG. 13 illustrates a back bias contact 90that is in electrical communication with the metal nitride 30 positionedin the channel portion of the fin structures 45 provides an electrodefor enabling back bias of the FinFET. In some embodiments, the back biascontact 90 should be deep in contact with the dopant region 2. As thedopant region 2 is across the entire active device region 95, the metalnitride 30 within the active device region 95 is in contact at thebottom with the dopant region 2. Thus the metal nitride 30 has the backbias voltage on the back contact 90.

In some embodiments, the method described above provides a semiconductordevice, e.g., FinFET, that includes a metal nitride 30 present centrallywithin a split portion of a channel region portion of a fin structure 45to apply a back bias to the semiconductor device. In one embodiment, thesemiconductor device includes a fin structure 45 comprising a splitportion, and a metal nitride 30 positioned in the split portion of achannel region of the fin structure. The semiconductor device mayfurther include a source region 70 including a first end of the splitportion of the fin structure that does not include the metal nitride;and a drain region 70 including a second end of the split portion of thefin structure that does not include the metal nitride. The first end andthe second end of the split portion are on opposing sides of the channelregion. A gate structure 75, 80 is present on the channel region of thefin structure. The metal nitride 30 is selected from the groupconsisting of titanium nitride, tantalum nitride, tungsten nitride andcombinations thereof. A high-k dielectric layer 20 can be presentbetween the metal nitride 30 and sidewalls of the fin structure 45 thatare present in the split portion of the fin structure in the channelregion. A dielectric cap 35 can be present between the metal nitride 30and the gate structure 75, 80.

The methods and structures that have been described above with referenceto FIGS. 1-13 may be employed in any electrical device includingintegrated circuit chips. The integrated circuit chips including thedisclosed structures and formed using the disclosed methods may beintegrated with other chips, discrete circuit elements, and/or othersignal processing devices as part of either (a) an intermediate product,such as a motherboard, or (b) an end product. The end product can be anyproduct that includes integrated circuit chips, including computerproducts or devices having a display, a keyboard or other input device,and a central processor.

While the methods and structures of the present disclosure have beenparticularly shown and described with respect to preferred embodimentsthereof, it will be understood by those skilled in the art that theforegoing and other changes in forms and details may be made withoutdeparting from the spirit and scope of the present disclosure. It istherefore intended that the present disclosure not be limited to theexact forms and details described and illustrated, but fall within thescope of the appended claims.

1. A method of forming a semiconductor device comprising: forming atrench in a substrate; forming a metal nitride in the trench; forming asplit fin structure from the substrate, wherein the metal nitride ispositioned in a split portion of the fin structure; removing the metalnitride from a source region and drain region portion of the split finstructure, wherein the metal nitride remains in a channel region portionof the split fin structure; and forming a gate structure on the channelregion portion of the split fin structure.
 2. The method of claim 1,wherein forming the trench comprises: forming a mandrel on thesubstrate; forming mandrel spacers on sidewalls of openings in themandrel; and etching the substrate using the mandrel and the mandrelspacers as an etch mask to form the trench in the substrate.
 3. Themethod of claim 2, wherein forming the metal nitride in the trenchcomprises: forming a high-k dielectric layer on sidewalls of the trench;depositing the metal nitride in the trench; and recessing the metalnitride to have an upper surface that is below an upper surface of thesubstrate.
 4. The method of claim 3 further comprising forming adielectric cap atop the recessed metal nitride that is recessed withinthe trench and removing the mandrel.
 5. The method of claim 4, formingthe split fin structure from the substrate comprises: etching thesubstrate using the dielectric cap and the mandrel spacers as an etchmask; forming isolation regions between the split fin structures;removing the mandrel spacers and a portion of the dielectric cap; andrecessing the isolation regions to reveal sidewalls of the split finstructure.
 6. The method of claim 5 further comprising forming asacrificial gate structure on the channel region portions of the splitfin structure.
 7. The method of claim 6, wherein said removing the metalnitride from the source region and drain region portion of the split finstructure comprises an etch process that removes the metal nitrideselectively to the sacrificial gate structure.
 8. The method of claim 7further comprising forming epitaxial source and drain region portions onthe source region and drain region portion of the split fin structure.9. The method of claim 8, wherein the gate structure is a functionalgate structure, and forming the functional gate structure comprises:forming an interlevel dielectric layer on the epitaxial source and drainregion portions having an upper surface coplanar with an upper surfaceof the sacrificial gate structure; removing the sacrificial gatestructure with an etch that is selective to the channel region portionof the split fin structure including the metal nitride; forming a high-kmetal gate stack on the channel region portion of the split finstructure; and forming a conductive fill atop the high-k metal gatestack.
 10. The method of claim 1, wherein back bias is applied to thesemiconductor device using the metal nitride in the split fin structureas an electrode.
 11. A method of forming the semiconductor devicecomprising: forming a trench in a substrate; forming a metal nitride inthe trench; forming a split fin structure from the substrate, whereinthe metal nitride is positioned in the split portion of the finstructure; removing the metal nitride from a source region and drainregion portion of the split fin structure, in which the metal nitrideremains in a channel region portion of the split fin structure; andforming a gate structure on the channel region portion of the finstructure, wherein a back bias is applied to the semiconductor deviceusing the metal nitride in the split fin structure as an electrode. 12.The method of claim 11, wherein the metal nitride is selected from thegroup consisting of titanium nitride, tantalum nitride, tungsten nitrideand combinations thereof.
 13. The method of claim 12, wherein formingthe metal nitride in the trench comprises; forming a mandrel on asubstrate; forming mandrel spacers on sidewalls of openings in themandrel; etching the substrate using the mandrel and the mandrel spacersas an etch mask to form the trench in the substrate; forming a high-kdielectric layer on sidewalls of the trench; depositing the metalnitride in the trench; and recessing the metal nitride to have an uppersurface that is below an upper surface of the substrate.
 14. The methodof claim 13 further comprising forming a dielectric cap atop therecessed metal nitride that is recessed within the trench and removingthe mandrel.
 15. The method of claim 14, forming the split fin structurefrom the substrate comprises: etching the substrate using the dielectriccap and the mandrel spacers as an etch mask; forming isolation regionsbetween the split fin structures; removing the mandrel spacers and aportion of the dielectric cap; and recessing the isolation regions toreveal sidewalls of the split fin structure. 16.-20. (canceled)